1. Field of the Invention
The present invention relates to method of forming a bypass circuit on a metal-oxide semiconductor (MOS) transistor, and more specifically, to a method of forming a bypass circuit for reducing plasma damage to a gate oxide of the MOS transistor.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) is a common electrical device used in integrated circuits. The MOS transistor is a unit, having four nodes, formed by a gate, a source and a drain. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digitalized solid switch applied on various integrated circuits of memory or logic devices.
Please refer to FIG. 1 to FIG. 4 of cross-sectional views of manufacturing a MOS transistor according to the prior art. As shown in FIG. 1, a silicon substrate 12, a gate oxide layer 14 and a gate 16 are formed, respectively, on a semiconductor wafer 10.
As shown in FIG. 2, a first ion implantation process 18 is performed to form two doped areas, employed as a lightly doped drain (LDD) 22 of the MOS transistor, located on either side of the gate 16 on the surface of the silicon substrate 12. The LDD 22 is also called a source-drain extension (SDE).
As shown in FIG. 3, a spacer 24, comprising an insulating material, is then formed on either vertical wall of the gate 16. As shown in FIG. 4, a second ion implantation process 26 is performed to form two doped areas, employed as a source 27 and a drain 28 of the MOS transistor, positioned on portions of the silicon substrate 12 adjacent to the spacer 24 to complete the manufacturing of the MOS transistor.
Please refer to FIG. 5 of the cross-sectional view of performing a self-alignment silicide process, which is frequently performed after the formation of the MOS transistor to reduce the contact resistance of each silicon surface on the MOS transistor, on a MOS transistor. As shown in FIG. 5, a silicide layer 32 is formed on the surfaces of the gate 16, the source 27 and the drain 28 of the MOS transistor after the self-alignment silicide process.
However, a huge amount of ions accumulate in the gate 16 as a result of ultraviolet (UV) radiation during a plasma etching, ion bombardment and photo process. The accumulated ions may penetrate from the gate 16 into the gate oxide layer 14 and the silicon substrate 12, causing the antenna effect that leads to the degradation of the gate oxide layer 14, which is called plasma process induced damage (PPID). Consequently, the electrical performance of the MOS transistor is flawed.
It is therefore a primary object of the present invention to provide a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor, in order to prevent the gate oxide layer of the MOS transistor from the plasma process induced damage (PPID).
According to the claimed invention, the MOS transistor is positioned on a substrate of a semiconductor wafer. A dielectric layer is formed to cover the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer down to a gate on the surface of the MOS transistor, and to simultaneously form a second contact hole through the dielectric layer down to an n-well in the substrate. A bypass circuit and a fusion area are formed to electrically connect the MOS transistor and the n-well thereafter. The bypass circuit comprises a metal layer and is positioned on the dielectric layer and on both the first and second contact holes, and the fusion area is composed of polysilicon or a narrow line. The fusion area is electrically cut off by performing a thermal process or by using a laser beam after the formation of the MOS transistor.
It is an advantage of the present invention against the prior art that a bypass circuit is formed to electrically connect the MOS transistor and the n-well, so that accumulated ions in the gate oxide, as a result of ultraviolet (UV) radiation during the plasma etching, ion bombardment and photo process, is transferred to the n-well via the bypass circuit so as to neutralize the ions in the n-well. Therefore, the antenna effect is prevented and the plasma process induced damage to the gate oxide is reduced as well.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.